integrated device technology, inc. military and commercial temperature ranges april 1994 1994 integrated device technology, inc. 7.22 dsc-4603/2 idt54/74fct841a/b/c high-performance cmos bus interface latches features: equivalent to amd? am29841-46 bipolar registers in pinout/function, speed and output drive over full tem- perature and voltage supply extremes idt54/74fct841a equivalent to fast ? speed idt54/74fct841b 25% faster than fast idt54/74fct841c 40% faster than fast buffered common latch enable, clear and preset inputs ? ol = 48ma (commercial) and 32ma (military) clamp diodes on all inputs for ringing suppression cmos power levels (1mw typ. static) ttl input and output level compatible cmos output level compatible substantially lower input current levels than amd? bipolar am29800 series (5 m a max.) product available in radiation tolerant and radiation enhanced versions military product compliant to mil-std-883, class b description: the idt54/74fct800 series is built using an advanced dual metal cmos technology. the idt54/74fct840 series bus interface latches are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/ data paths or buses carrying parity. the idt54/74fct841 is a buffered, 10-bit wide version of the popular ?73 function. all of the idt54/74fct800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. all inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high-imped- ance state. 1 2607 drw 01 functional block diagram d 0 d clr y 0 le q p clr le oe pre d n d clr y n le q p the idt logo is a registered trademark of integrated device technology, inc. fast is a trademark of national semiconductor co.
7.22 2 idt54/74fct841a/b/c high-performance cmos bus interface latches military and commercial temperature ranges pin configurations oe d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 gnd y 0 y 1 y 2 y 3 y 4 y 6 le y 5 y 7 v cc p24-1 d24-1 e24-1 & so24-2 d 8 d 9 y 8 y 9 dip/cerpack/soic top view index d 2 y 2 y 3 y 4 nc y 5 oe d 1 nc v cc y 0 d 8 gnd le y 9 y 8 lcc top view l28-1 d 3 d 4 nc d 5 d 6 d 7 d 0 y 1 y 6 y 7 d 9 nc 32 20 19 1 4 5 6 7 8 18 17 16 15 14 9 10 11 12 13 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20 11 12 21 22 23 24 2607 drw 02 2607 drw 03 pin description function table (1) name i/o description clr i when clr is low, the outputs are low if oe is low. when clr is high, data can be entered into the latch. d i i the latch data inputs. le i the latch enable input. the latches are transparent when le is high. input data is latched on the high-to-low transition. y i o the 3-state latch outputs. oe i the output enable control. when oe is low, the outputs are enabled. when oe is high, the outputs (y i ) are in the high-impedance (off) state. pre i preset line. when pre is low, the outputs are high if oe is low. preset overrides clr . 2607 tbl 01 inputs inter- nal out- puts clr clr pre pre oe oe le d i q i y i function h h h x x x z high z h h h h l l z high z h h h h h h z high z h h h l x nc z latched (high z) h h l h l l l transparent h h l h h h h transparent h h l l x nc nc latched h l l x x h h preset l h l x x l l clear l l l x x h h preset l h h l x l z latched (high z) h l h l x h z latched (high z) note: 2607 tbl 02 1. h = high, l = low, x = dont care, nc = no change, z = high impedance
idt54/74fct841a/b/c high-performance cmos bus interface latches military and commercial temperature ranges 7.22 3 absolute maximum ratings (1) symbol rating commercial military unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 C0.5 to +7.0 v v term (3) terminal voltage with respect to gnd C0.5 to v cc C0.5 to v cc v t a operating temperature 0 to +70 C55 to +125 c t bias temperature under bias C55 to +125 C65 to +135 c t stg storage temperature C55 to +125 C65 to +150 c p t power dissipation 0.5 0.5 w i out dc output current 120 120 ma note: 2607 tbl 03 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. no terminal voltage may exceed v cc by +0.5v unless otherwise noted. 2. input and v cc terminals only. 3. outputs and i/o terminals only. capacitance (t a = +25 c, f = 1.0mhz) symbol parameter (1) conditions typ. max. unit c in input capacitance v in = 0v 6 10 pf c out output capacitance v out = 0v 8 12 pf note: 2607 tbl 04 1. this parameter is measured at characterization but not tested. dc electrical characteristics over operating range following conditions apply unless otherwise specified: v lc = 0.2v; v hc = v cc C 0.2v commercial: t a = 0 c to +70 c, v cc = 5.0v 5%; military: t a = C55 c to +125 c, v cc = 5.0v 10% notes: 2607 tbl 05 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient and maximum loading. 3. not more than one output should be shorted at one time. duration of the short circuit test should not exceed one second. 4. this parameter is guaranteed but not tested. symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high level guaranteed logic high level 2.0 v v il input low level guaranteed logic low level 0.8 v i i h input high current v cc = max. v i = v cc 5 m a v i = 2.7v 5 (4) i i l input low current v i = 0.5v C5 (4) v i = gnd C5 i ozh off state (high impedance) v cc = max. v o = v cc 10 m a output current v o = 2.7v 10 (4) i ozl v o = 0.5v C10 (4) v o = gnd C10 v ik clamp diode voltage v cc = min., i n = C18ma C0.7 C1.2 v i os short circuit current v cc = max. (3) , v o = gnd C75 C120 ma v oh output high voltage v cc = 3v, v in = v lc or v hc , i oh = C32 m av hc v cc v v cc = min. i oh = C300 m av hc v cc v in = v ih or v il i oh = C15ma mil. 2.4 4.3 i oh = C24ma com'l. 2.4 4.3 v ol output low voltage v cc = 3v, v in = v lc or v hc , i ol = 300 m a gnd v lc v v cc = min. i ol = 300 m a gnd v lc (4) v in = v ih or v il i ol = 32ma mil. 0.3 0.5 i ol = 48ma com'l. 0.3 0.5
7.22 4 idt54/74fct841a/b/c high-performance cmos bus interface latches military and commercial temperature ranges power supply characteristics v lc = 0.2v; v hc = v cc C 0.2v notes: 2607 tbl 06 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at vc c = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v); all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f cp /2 + f i n i ) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f cp = clock frequency for register devices (zero for non-register devices) f i = input frequency n i = number of inputs at f i all currents are in milliamps and all frequencies are in megahertz. symbol parameter test conditions (1) min. typ. (2) max. unit i cc quiescent power supply current v cc = max. v in 3 v hc ; v in v lc 0.2 1.5 ma d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 2.0 ma i ccd dynamic power supply current (4) v cc = max. outputs open oe = gnd le = v cc one input toggling 50% duty cycle v in 3 v hc v in v lc 0.15 0.25 ma/ mhz i c total power supply current (6) v cc = max. outputs open fi = 10mhz 50% duty cycle v in 3 v hc v in v lc (fct) 1.7 4.0 ma oe = gnd le = v cc one bit toggling v in = 3.4v v in = gnd 2.0 5.0 v cc = max. outputs open fi = 2.5mhz 50% duty cycle v in 3 v hc v in v lc (fct) 3.2 6.5 (5) oe = gnd le = v cc eight bits toggling v in = 3.4v v in = gnd 5.2 14.5 (5)
idt54/74fct841a/b/c high-performance cmos bus interface latches military and commercial temperature ranges 7.22 5 switching characteristics over operating range fct841a fct841b fct841c com'l. mil. com'l. mil. com'l. mil. symbol parameter conditions (1) min. (2) max. min. (2) max. min. (2) max. min. (2) max. min. (2) max. min. (2) max. unit t plh t phl propagation delay d i to y i (le = high) c l = 50pf r l = 500 w 1.5 9.0 1.5 10.0 1.5 6.5 1.5 7.5 1.5 5.5 1.5 6.3 ns c l = 300pf (4) r l = 500 w 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 1.5 13.0 1.5 15.0 t plh t phl propagation delay le to y i c l = 50pf r l = 500 w 1.5 12.0 1.5 13.0 1.5 8.0 1.5 10.5 1.5 6.4 1.5 6.8 ns c l = 300pf (4) r l = 500 w 1.5 16.0 1.5 20.0 1.5 15.5 1.5 18.0 1.5 15.0 1.5 16.0 t plh propagation delay, pre to y i c l = 50pf 1.5 12.0 1.5 14.0 1.5 8.0 1.5 10.0 1.5 7.0 1.5 9.0 ns t phl r l = 500 w 1.5 14.0 1.5 17.0 1.5 10.0 1.5 13.0 1.5 9.0 1.5 12.0 t phl propagation delay, clr to y i 1.5 13.0 1.5 14.0 1.5 10.0 1.5 11.0 1.5 9.0 1.5 10.0 ns t plh 1.5 14.0 1.5 17.0 1.5 10.0 1.5 10.0 1.5 9.0 1.5 9.0 t pzh t pzl output enable time oe to y i c l = 50pf r l = 500 w 1.5 11.5 1.5 13.0 1.5 8.0 1.5 8.5 1.5 6.5 1.5 7.3 ns c l = 300pf (4) r l = 500 w 1.5 23.0 1.5 25.0 1.5 14.0 1.5 15.0 1.5 12.0 1.5 13.0 t phz t plz output disable time oe to y i c l = 5pf (4) r l = 500 w 1.5 7.0 1.5 9.0 1.5 6.0 1.5 6.5 1.5 5.7 1.5 6.0 ns c l = 50pf r l = 500 w 1.5 8.0 1.5 10.0 1.5 7.0 1.5 7.5 1.5 6.0 1.5 6.3 t su data to le set-up time c l = 50pf 2.5 2.5 2.5 2.5 2.5 2.5 ns t h data to le hold time r l = 500 w 2.5 3.0 2.5 2.5 2.5 2.5 ns t w le pulse width (3) high 4.0 5.0 4.0 4.0 4.0 4.0 ns t w pre pulse width (3) low 5.0 7.0 4.0 4.0 4.0 4.0 ns t w clr pulse width (3) low 4.0 5.0 4.0 4.0 4.0 4.0 ns t rem recovery time pre to le 4.0 4.0 4.0 4.0 4.0 4.0 ns t rem recovery time clr to le 3.0 3.0 3.0 3.0 3.0 3.0 ns notes: 2607 tbl 07 1. see test circuit and waveforms. 2. minimum limits are guaranteed but not tested on propagation delays. 3. these parameters are guaranteed but not tested. 4. these conditions are guaranteed but not tested.
7.22 6 idt54/74fct841a/b/c high-performance cmos bus interface latches military and commercial temperature ranges pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. test circuits and waveforms test circuits for all outputs set-up, hold and release times pulse width switch position test switch open drain disable low closed enable low all other tests open definitions: 2607 tbl 08 c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. enable and disable times propagation delay notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns 2607 drw 04
idt54/74fct841a/b/c high-performance cmos bus interface latches military and commercial temperature ranges 7.22 7 ordering information idt xx temp. range xxxx device type x package x process blank b p d e l so 841a 841b 841c commercial mil-std-883, class b plastic dip cerdip cerpack leadless chip carrier small outline ic 10-bit non-inverting latch 54 74 C55 c to +125 c 0 c to +70 c fct 2607 drw 05
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